 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET Part No. Package Code No. AN12959A UBGA021-W-2525AEA Publication date: October 2008 SDE00028BEB 1 AN12959A Contents Overview Features Package Type ........................................................................................................................... 3 ........................................................................................................................... 3 ...................................................................................................................... 3 ............................................................................................................................ 3 Applications ............................................................................................................................... 3 .................................................................................................................. 5 .................................................................................................... 6 ...................................................................................................... 7 ............................................................. 9 Application Circuit Example (Block Diagram) ............................................................................. 4 Pin Descriptions Absolute Maximum Ratings Electrical Characteristics Technical Data Usage Notes Operating Supply Voltage Range ............................................................................................. 6 Electrical Characteristics (Reference values for design) .................................................................................................................. 10 ...................................................................................................................... 26 SDE00028BEB 2 AN12959A AN12959A I2C bus control compatible AGC built-in stereo BTL amplifier IC (For driving a piezoelectric speaker) Overview AN12959A has a built-in AGC function in a stereo BTL amplifier for driving a piezoelectric speaker to prevent noise at output clip. And I2C bus control method is applied in switching of each mode like some Standby function is turned ON/OFF. Features The piezoelectric speaker can be driven by applying the circuit of high withstand voltage power amplifier. On level in AGC can be selected by controlling I2C bus. Attack and recovery times in AGC can be selected by controlling I2C bus. Resistance and capacitor, which were used for conventional analog AGC aren't needed anymore. I2C is controlled almost in the same way as those of AN12979A/AN12978A. Shut-down function is mounted. Amplifier gain switching The input circuit constructs a bus boost circuit easily and improves the sound quality of the piezoelectric speaker. Applications Audio amplifier for mobile, such as a cellular phone Package 21 pin plastic quad 5 column BGA package (0.5 mm pitch) Type Silicon Monolithic Bi-CMOS IC SDE00028BEB 3 AN12959A Application Circuit Example (Block Diagram) VCC = 3 V VREF 7.5 to 10 Piezoelectric speaker GND ROUT_POS E2 N.C. D2 +14 dB D3 N.C. C3 E3 1 F VCC E4 E5 GND 1 F GND_SPR E1 ROUT_NEG D1 7.5 to 10 VCC_SP = 6.1 V VCC_SP C1 1 F VREF_SP 1 F Piezoelectric speaker +14 dB Gain Select +6 dB / 0 dB AGC VREG (5 V) AGC DET AGC +14 dB D4 PREOUT_R + - 10 k D5 FB_R 1500 pF 10 k INPUT_R 0.1 F 10 k INPUT_L 0.1 F C2 7.5 to 10 LOUT_NEG B1 +14 dB +6 dB / 0 dB Gain Select I2C-BUS Control - + C5 FB_L 10 k C4 PREOUT_L 1500 pF GND_SPL A1 A5 GND A2 7.5 to 10 LOUT_POS B2 N.C. 0.1 F * VCC_D B3 A3 S.D VCC_D B4 SDA 2.2 k A4 SCL 2.2 k Operate Shutdown 1 F VCC_D = 1.8 V B3 pin Operate voltage VCC_D = 1.8 V Operate > 1.62 V Shut-down < 0.18 V VCC_D = 2.6 V Operate > 2.34 V Shut-down < 0.26 V Note) 1. This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. 2. *:The threshold voltage at Pin B3 has the VCC_D dependency. SDE00028BEB 4 AN12959A Pin Descriptions Pin No. A1 A2 A3 A4 A5 B1 B2 B3 B4 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 Pin name GND_SPL LOUT_POS VCC_D SCL GND LOUT_NEG N.C. S.D SDA VCC_SP VREF_SP N.C. PREOUT_L FB_L ROUT_NEG N.C. GND PREOUT_R FB_R GND_SPR ROUT_POS VREF VCC GND Type Ground Output Power Supply Input Ground Output -- -- Input / Output Power Supply Input -- Output Input Output -- Ground Output Input Ground Output Input Power Supply Ground Grounding (For speaker L-channel) Speaker output L-channel (+) VCC_D for logic circuit SCL Grounding Speaker output L-channel(-) N.C. Shut-down pin SDA VCC_SP for the circuit of speaker output Reference voltage pin for the circuit of speaker output N.C. First amplifier output L-channel First amplifier negative feedback input L-channel Speaker output R-channel(-) N.C. Grounding First amplifier output R-channel First amplifier negative feedback input R-channel Grounding (For speaker R-channel) Speaker output R-channel(+) Reference voltage pin Power supply VCC Grounding Description SDE00028BEB 5 AN12959A Absolute Maximum Ratings A No. Parameter Symbol VCC 1 Supply voltage VCC_D VCC_SP 2 3 4 5 6 Supply current Input voltage Power dissipation Operating ambient temperature Storage temperature ICC VI PD Topr Tstg Rating 5.0 3.6 12 -- -- 113 -20 to +70 -55 to +150 A V mW C C -- -- *2 *3 *3 V *1 Unit Note Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 70C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the * PD - Ta diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25C. Operating Supply Voltage Range Parameter Symbol VCC Supply voltage range VCC_D VCC_SP Range 2.7 to 4.5 1.7 to 2.6 1.7 to 3.3 5.9 to 11.5 V Unit Note *1 *1, *2 *1, *3 *1 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The values under FAST- mode. *3: The values under STANDARD- mode. SDE00028BEB 6 AN12959A Electrical Characteristics at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V Note) Ta = 25C2C unless otherwise specified. B No. Circuit Current 1 2 3 4 5 6 7 8 9 Parameter Symbol Conditions Limits Min Typ Max Unit Note Circuit current 1A at non-signal (VCC) Circuit current 2A at non-signal (VCC_SP) Circuit current 3A at non-signal (VCC_D) Circuit current 1B at non-signal (VCC) Circuit current 2B at non-signal (VCC_SP) Circuit current 3B at non-signal (VCC_D) Circuit current 1C at non-signal (VCC) Circuit current 2C at non-signal (VCC_SP) Circuit current 3C at non-signal (VCC_D) IVCC1A IVCC2A IVCC3A IVCC1B IVCC2B IVCC3B IVCC1C IVCC2C IVCC3C Non-signal, STB = OFF, SP = ON, AGC = ON Non-signal, STB = OFF, SP = ON, AGC = ON Non-signal, STB = OFF, SP = ON, AGC = ON Non-signal, STB = ON, SP = OFF, AGC = ON Non-signal, STB = ON, SP = OFF, AGC = ON Non-signal, STB = ON, SP = OFF, AGC = ON Non-signal, STB = OFF, SP = OFF, AGC = ON Non-signal, STB = OFF, SP = OFF, AGC = ON Non-signal, STB = OFF, SP = OFF, AGC = ON -- -- -- -- -- -- -- -- -- 0.5 9.0 0.1 0.1 0.1 0.1 0.5 4.5 0.1 1.0 18 10 1.0 1.0 1.0 1.0 6.5 10 mA mA A A A A mA mA A -- -- -- -- -- -- -- -- -- I/O Characteristics 10 SP reference output level 11 SP reference output distortion 12 SP reference output noise voltage 13 Output level at SP Save VSPOL VSPOR THSPOL THSPOR Vin = -26.0 dBV, f = 1 kHz, RL = 100 Vin = -26.0 dBV, f = 1 kHz, RL = 100 , to THD 5th -1.0 -- -- -- 0.0 0.07 -75 -114 1.0 0.5 -68 -90 dBV % dBV dBV -- -- -- -- VNSPOL Non-Signal VNSPOR using A curve filter VSSPOL VSSPOR Vin = -26.0 dBV, f = 1 kHz, RL = 100 , using A curve filter 14 SP AGC output level Vin = -6.0 dBV, f = 1 kHz, VSPOA1L RL = 100 , VCC_SP = 10 V, VSPOA1R AGC - SELECT = [010] 12.9 13.9 14.9 dBV -- SDE00028BEB 7 AN12959A Electrical Characteristics at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V (continued) Note) Ta = 25C2C unless otherwise specified. B No. I2C interface 15 16 17 18 19 Parameter Symbol Conditions Limits Min Typ Max Unit Note SCL, SDA signal input Low level SCL, SDA signal input High level SDA signal output Low Level SCL, SDA signal input current Max. frequency of SCL signal allowable to input VIL VIH VOL Ii fSCL -- -- Open corrector, sync current: 3mA Input voltage 0.1 V to 1.7 V -- -0.5 0.7 x VCC_D 0 -10 0 -- -- -- -- -- 0.3 x VCC_D VCC_D + 0.5 0.2 x VCC_D 10 400 V V V A kHz -- -- -- -- -- The threshold voltage at Pin B3 20 21 Shut-down input Low level Shut-down input High level Vsdlth Vsdhth -- -- -- 0.9 x VCC_D -- -- 0.1 x VCC_D -- V V -- -- SDE00028BEB 8 AN12959A Electrical Characteristics (Reference values for design) at VDD = VMSP = VMAC = VMST = VMBX = VMLO = 5 V VREF = 1.65 VSTBY = 3.3 V Note) Ta = 25C2C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. B No. I2C interface 31 32 33 34 35 36 37 38 39 40 Parameter Symbol Conditions Limits Min Typ Max Unit Note Bus free time between stop and start conditions Setup time of start condition Hold time of start condition Low period of SCL clock High period of SCL clock Rising time of SDA, SCL signal Falling time of SDA, SCL signal Data setup time Data hold time Setup time of stop condition tBUF tSU;STA tHD;STA tLow tHigh tR tF tSU;DAT tHD;DAT tSU;STO -- -- -- -- -- -- -- -- -- -- 1.3 0.6 0.6 1.3 0.6 -- -- 0.1 0 0.6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.3 0.3 -- 0.9 -- s s s s s s s s s s *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level. *3: VILmax is the maximum limit of the signal input low level. START CONDITION VIHmin Repeated START STOP CONDITION CONDITION START CONDITION SDA tF tLow tR tSU;DAT tF (*2) VILmax(*3) tBUF tR tHD;STA SCL tHD;STA tHD;DAT tHigh tSU;STA tSU;STO SDE00028BEB 9 AN12959A Technical Data I2C-bus mode 1.Write mode SDA SCL SLAVE ADDRESS SUB ADDRESS DATA ACK ACK STOP CONDITION START CONDITION ACK 10110110 B 6 00000001 0 1 Example of transmission messages 10000000 8 0 Two transmission messages (i.e. the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. SDE00028BEB 10 AN12959A Technical Data (continued) I2C-bus mode (continued) 1.Write mode (continued) (a) I2C-bus PROTOCOL Slave address: 10110110 (B6Hex) Format (Normal) S Slave address WA Sub-address A Data byte A P Stop condition Start condition Write Acknowledge bit Mode: 0 (b) Auto increment Sub-address 0*Hex: Auto increment mode (When the data is sent in sequence, the sub-address will change one by one and the data will be input.) Auto increment mode S Slave address WA Sub-address A Data 1 A Data 2 A Data n A P (c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0(Note.1) will be absolutely "0", when the power is turned ON. (d) Sub-address Byte and Data Byte Format Subaddress *0Hex MSB D7 GAIN 0 +20 dB 1 +26 dB AGC-ON data bit3 0 (*1,*2) D6 0 (*1) AGC-ON data bit2 0 (*1,*2) D5 0 (*1) AGC-ON data bit1 0 (*1,*2) D4 0 (*1) AGC-REC data bit3 0 (*1,*2) Data byte D3 AGC 0 OFF 1 ON AGC-REC data bit2 0 (*1,*2) D2 SP Save 0 ON 1 OFF AGC-REC data bit1 0 (*1,*2) D1 Standby 0 ON 1 OFF AGC-ATT data bit2 0 (*1,*2) LSB D0 0 (*1) AGC-ATT data bit1 0 (*1,*2) *1Hex *2Hex Note) *1: <00Hex Register> D0, D4, D5, D6: Always set to "0" D1: Standby ON/OFF switch D2: D2: SP Save ON/OFF switch D3: AGC ON/OFF switch D7: GAIN +20 dB / +26 dB selection <01Hex Register> D0, D1: AGC-attack-time selection D2, D3, D4: AGC-recovery-time selection D5, D6, D7: AGC-on-level selection <02Hex Register> Always set to "0". (test & adjust mode). *2: Please use these bit only Data = "0", because they are used by our company's final test and fine-tuning AGC-on level. Note that Data = "1" is not shut-down mode. SDE00028BEB 11 AN12959A Technical Data (continued) I2C-bus mode (continued) 1. Write Mode (continued) (e) AGC-attack-time selection Write 01Hex Register D1 0 0 1 1 D0 0 1 0 1 Attack time 0.5 ms 1 ms 2 ms 4 ms (f) AGC-recovery-time selection Write 01Hex Register D4 0 0 0 0 1 1 D3 0 0 1 1 0 0 D2 0 1 0 1 0 1 Recovery time 1.0 s 1.5 s 2.0 s 3.0 s 4.0 s 6.0 s (g) AGC-on-level selection at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V *1 Write 01Hex Register D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 AGC On Level 12.6 dBV 13.2 dBV 13.9 dBV 14.5 dBV 15.1 dBV 15.6 dBV 16.1 dBV 16.6 dBV Output (V[p-p]) 12 V[p-p] 13 V[p-p] 14 V[p-p] 15 V[p-p] 16 V[p-p] 17 V[p-p] 18 V[p-p] 19 V[p-p] VCC_SP (Reference) *2 8.5 V 9.0 V 9.5 V 10.0 V 10.5 V 11.0 V 11.0 V *3 11.0 V *3 Note) *1: At the time of VCC_SP = 6.1 V, output is clipped, excessive clip in AGC OFF can be prevented. *2: The supply voltage of VCC_SP at which output is not clipped. *3: Output is clipped a little. (h) Amp. gain selection at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V Write 00Hex Register D7 0 1 20 dB 26 dB Gain SDE00028BEB 12 AN12959A Technical Data (continued) I2C-bus mode (continued) 2. Read Mode (a) I2C-bus PROTOCOL Slave address 10110111 (B7Hex) Format S Slave address R A Data 0 A Data 1 A Data 2 A P Read Mode: 1 Note) At the slave address input, it is sequentially output from Data 0. There is no necessity for inputting the sub-address. (b) Sub-address Byte and Data Byte Format MSB D7 Data 0 Data byte D6 D5 D4 D3 D2 D1 LSB D0 Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex Latch data D7 Latch data D6 Latch data D5 Latch data D4 Latch data D3 Latch data D2 Latch data D1 Latch data D0 Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex Latch data D7 Latch data D6 Latch data D5 Latch data D4 Latch data D3 Latch data D2 Latch data D1 Latch data D0 Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex Latch data D7 Latch data D6 Latch data D5 Latch data D4 Latch data D3 Latch data D2 Latch data D1 Latch data D0 Data 1 Data 2 This IC is compatible with I2C-bus format. Purchase of Panasonic I2C Components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specifications as defined by Philips. Operating temperature guarantee of I2C-bus Control The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns. SDE00028BEB 13 AN12959A Technical Data (continued) I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VCC_D (1.8 V) Impedance Description S.D B3 Hi-Z B3 Shut-down mode pin Input impedance Please do not make it open, because the = Hi-Z open S.D pin is not fixed. VCC_D (1.8 V) SCL A4 Hi-Z A4 Input impedance 2 I C-BUS SCL pin = Hi-Z VCC_D (1.8 V) SDA B4 Hi-Z B4 Input impedance 2 I C-BUS SDA pin = Hi-Z GND VCC_D A3 1.8 V(typ.) -- -- Power supply pin for I2C-BUS SDE00028BEB 14 AN12959A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VCC_SP(6.1 V) Impedance Description LOUT_POS A2 DC 2.7 V 4k 20k A2 Output impedance = Equal to or less than 1 L-channel positive speaker output pin GND_SPL GND_SPL A1 DC 0 V VCC_SP(6.1 V) -- -- Ground pin for L-channel speaker output LOUT_NEG B1 DC 2.7 V 4k 20k B1 Output impedance = Equal to or less than 1 L-channel negative speaker output pin GND_SPL VCC_SP C1 6.1 V(typ.) -- -- Power supply pin for speaker output SDE00028BEB 15 AN12959A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Impedance Description VCC_SP(6.1 V) ROUT_NEG 20k D1 DC 2.7 V 4k D1 Output impedance = Equal to or less R-channel negative speaker output pin than 1 GND_SPR GND_SPR E1 DC 0 V VCC_SP(6.1 V) -- -- GND pin for R-channel speaker output ROUT_POS 20k E2 DC 2.7 V 4k E2 Output impedance = Equal to or less R-channel positive speaker output pin than 1 GND_SPR VCC_SP(6.1 V) VREF_SP C2 DC 2.7 V C2 10k 1k 300k The reference voltage terminal for determining DC bias of the output stage Input impedance of a speaker amplifier system. = About 150 k Please connect an external capacitor to remove a ripple. 300k SDE00028BEB 16 AN12959A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. A5 E5 D3 E4 Waveform and voltage GND Internal circuit Impedance Description -- DC 0 V VCC -- 3.0 V(typ.) VREG (5 V) -- Ground pin -- Power supply pin VREF E3 DC 2.5 V E3 150k Input impedance = About 75 k The reference voltage terminal for determining DC bias of the input stage of a speaker amplifier system. Please connect an external capacitor to remove a ripple. 150k VREG (5 V) PREOUT_R D4 DC 2.5 V D4 Output terminal of R-channel input Output impedance amplifier of speaker amplifier system. = Equal to or less Please connect external resistance for the than 10 gain setting. SDE00028BEB 17 AN12959A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage VREG (5 V) Internal circuit Impedance Description FB_R D5 DC 2.5 V D5 Input impedance = Hi-Z Feedback terminal of R-channel input amplifier of speaker amplifier system. The gain of the R-channel input amplifier can be set by connecting an external resistance between Pin D4 and Pin D5. GND VREG (5 V) FB_L C5 DC 2.5 V C5 Input impedance = Hi-Z Feedback terminal of L-channel input amplifier of speaker amplifier system. The gain of the L-channel input amplifier can be set by connecting an external resistance between Pin C4 and Pin C5. GND VREG (5 V) PREOUT_L C4 DC 2.5 V C4 Output terminal of L-channel input Output impedance amplifier of speaker amplifier system. = Equal to or less Please connect external resistance for the than 10 gain setting. B2 C3 D2 N.C. -- Input impedance = Hi-Z Feedback terminal of R-channel input amplifier of speaker amplifier system. The gain of the R-channel input amplifier can be set by connecting an external resistance between Pin D4 and Pin D5. SDE00028BEB 18 AN12959A Technical Data (continued) Power supply and logic sequence Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1. The sequence of the power supply and each logic Please turn on the power supply first, and then get Standby OFF. VCC, VCC_SP, VCC_D, SD Power supply Off Off Off On Off Off On 30 ms or more * 0 ms or more The basic procedure at the power-on The power OFF condition. Both the Standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby OFF 4. SP_Save OFF 1. On On Off Standby On The basic procedure at the power-off 1. The power ON condition. Both the Standby and the SP_Save are in the OFF condition. 2. SP_Save ON (= Standby ON) 3. Standby ON 4. Power OFF SP_Save On After at least 30 ms has passed after the standby off, please off SP_Save. Please get Standby On simultaneously with or after SP_Save On. Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN_R and IN_L). It is a recommendation value in a constant given in the example of Application Circuit Example (Block Diagram). 2. The sequence of VCC and VCC_SP and VCC_D This IC does not have a rising and falling order in VCC, VCC_SP, and VCC_D. Rising and falling times of them are recommended 1 ms or more. On On Off VCC VCC_SP VCC_D Off 1 ms or more 1 ms or more SDE00028BEB 19 AN12959A Technical Data (continued) Explanation on mainly functions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 1. Power supply 1) Power supply for output amplifier The output amplifier operates with voltage applied to VCC_SP. When power supply is applied to only VCC_SP in AN12959A, the product does not operate. (In case where voltage is not applied to VCC and VCC_D), it gets in Standby condition. AN12959A output maximum amplitude VCC_SP - 1.3 V(typ.) 2) Power supply for control system The control system operates with power supply applied to VCC pin. (I2C logic, clock generation circuit, etc.) 3) Power supply for signal system The signal system operates with the internal regulator of 5 V. 5 V, reference voltage of the internal regulator is generated from VCC_SP using VCC power supply. By setting signal voltage at 5 V, the dynamic range of the signal can be secured sufficiently. When the gain of the input amplifier is 0 dB, clip occurs at the amplitude of 3 V[p-p] (typ.) in input signal. 4) Power supply for I2C interface I2C interface operates with power supply applied to VCC_D pin. I2C circuit operates with VCC. 5) High voltage at shut-down pin Please use the power supply applied to VCC_D or apply voltage from the outside. Threshold voltage depends on the voltage to VCC_D. SDE00028BEB 20 AN12959A Technical Data (continued) Explanation on mainly functions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 2. Speaker amplifier 1500 pF 10 k INPUT_L 0.1 F 10 k - + AGC DET +14 dB LOUT_NEG BTL: +6 dB AGC 0 dB +6 dB / 0 dB +14 dB LOUT_POS I2C Logic 1) the gain for a input amplifier can be set with an external resistance. Input impedance is also set with the external resistance. When the gain for the input amplifier is set at 0 dB, the total gain for the speaker amplifier is +26 dB or +20 dB (It can be selected with I2C). When the external resistance for the input amplifier is assumed as R1, R2, Gain = 20 log (R2 / R1) Zin = R1 R1 - + R2 In case of R1 = 10 k, R2 = 10 k with the constants in the above fig, the gain for the input amplifier is 0 dB and impedance is 10 k. During operation, keep the voltage of R1 and R2 at more than 5 k. 2) With an external capacity added to the input amplifier, LPF, which removes an unwanted high frequency element, can be constructed. When external resistance is assumed as R2, capacity as C2, fc = 1 / (2 x R2 x C2) C2 R2 - + In case of R2 = 10 k, C2 = 1500 pF with the constants in the above fig, Cut-off frequency, fc is 10.6 kHz. SDE00028BEB 21 AN12959A Technical Data (continued) Explanation on mainly functions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 2. Speaker amplifier (continued) 3) With the smaller capacity of the input AC coupling capacitor, HPF, which removes unwanted low frequency element, can be constructed. When input resistance is assumed as R1, and AC coupling capacitor as C1, R2 fc = 1 / (2 x R1 x C1) In case of R1 = 10 k, C1 = 0.1 F, cut-off frequency, fc is 160 Hz. In case of R1 = 10 k, C1 = 0.022 F, cut-of frequency, fc is 720 Hz. C1 0.1 F R1 - + 4) Bus Boost circuit can be constructed by adding capacity (RBB) and resistance (CBB) to the input amplifier. The frequency to increase 3 dB is assumed as fo Cf fo = Bus Boost Gain Ao = 1 / (2 x x Rf x CBB) 20 log ((Rf + RBB) / Rf) 20 log ((Rf + RBB) / Rin) Cin Rin Rf RBB CBB - + 3. Protection circuit for speaker amplifier 1) Thermal protection circuit The thermal protection circuit operates at the Tj of approximately 150C. The thermal protection circuit is reset automatically when the temperature drops. 2) Output pin short protection circuit Output pin-power supply line short protection Output-to-output pin short protection Output pin-GND line short protection If short-circuit is no longer detected, it will return automatically. Note) Operation is not guaranteed although the protection circuit is built in. Moreover, hundred percent inspection is not guaranteed. SDE00028BEB 22 AN12959A Technical Data (continued) Explanation on mainly functions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 4. Cautions 1) Cautions about AGC Signal output in the input amplifier is detected and converted to forward current. Compared this forward current with reference voltage, if the forward current is larger, AGC turns ON. When the frequency band of the speaker is narrower than that of the amplifier. If maximum input is made in low frequency band, AGC operates to decrease volume. Namely, low sound part is not heard from a speaker, but AGC reacts to low sound part to turn down the volume. Please carefully design so that the frequency bands is synchronized between the speaker and amplifier. Note) Frequency characteristics should be set not only for the speaker, but in the built-in condition. The below Graph shows when the values of resistance and capacity are changed. Frequency characteristics VccSP=9V Vin=-22dBV AGC OFF 15 10 Output level BV) 5 0 -5 -10 -15 0.01 Cin=0.1uF Cf=1500pF Rin=10K RF=10K CBB=0 RBB=0 Cin=0.039uF Cf=1500pF Rin=10K RF=5.6K CBB=0.015uF RBB=10K 0.1 1 Input frequency (kHz) 10 100 2) Cautions about VCC_SP ON/OFF With VCC in AN12959A always on, when VCC_SP is turned ON/OFF, I2C data is retained. When VCC_SP is turned ON OFF ON without I2C control, pop sound comes out, as starting time for the amplifier gets significantly long. (Input amplifier, AGC circuit, and standard voltage are provided by VCC_SP). Note) Please never fail to turn ON Standby and SP_Save with I2C first, and then turn OFF VCC_SP. Next, turn ON VCC_SP, and turn OFF Standby and SP_Save to operate amplifier with I2C. If Standby is switched from ON to OFF with I2C, the amplifier starts within a short time, as a circuit runs to quickly charge an external condenser connected to Vref pin. (When VCC_SP is turned ON OFF ON without Standby control, the circuit of fast charge does not run.) Please space the time of 30 ms from turning Standby ON OFF to SP_Save OFF. 3) Cautions about shut-down with SD pin During normal operation, when a shut-down pin is turned Low directly, shock noise comes out. As SP_Save is set in mute, first turn ON SP_Save, and then turn ON Standby to stop operation. Finally, set shut-down pin to Low. SDE00028BEB 23 AN12959A Technical Data (continued) Simulation of output current waveform Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. (There is twice as much difference as between current and voltage in a piezoelectric speaker per 1 channel.) A piezoelectric speaker of ceramic lamination type is used. Piezoelectric speaker Output current (Set at an absolute value.) Iout(max) = 250 mA 7.5 to 10 Output current 10 kHz, 15 V[p-p] Current 7.5 to 10 Output current (Set at an absolute value.) Iout(max) = 580 mA As resistance lies at output, the clip wave gets blunt in the capacity of resistance and speaker. Output waveform 10 kHz, 15 V[p-p] Output current (Set at an absolute value.) Iout(max) = 710 mA Output waveform 10 kHz, 15 V[p-p] No resistance at output If output waveform is clipped without resistance of more than 7.5 x 2 at amplifier output, excessive current runs. Please never fail to insert resistance in use. Excessive current can cause intermittent output signal with load-short protection operated. SDE00028BEB 24 AN12959A Technical Data (continued) PD Ta diagram SDE00028BEB 25 AN12959A Usage Notes 1. Please carry out the thermal design with sufficient margin such that the power dissipation will not be exceeded, based on the conditions of power supply, load and surrounding temperature. Although indicated also in the column of the maximum rating, the maximum rating becomes an instant and the marginal value which must not exceed. It sufficiently evaluates, and I use-wishdo so that it may not exceed certainly. Moreover, don't impress neither voltage nor current to PIN which is not indicated. It may destroy in both cases. 2. Please pay attention to the pattern layout in order to prevent damage due to short circuit between pins. In addition, for the pin configuration, please refer to the Pin Descriptions. 3. Please absolutely do not mount the LSI in the reverse direction on to the printed-circuit-board. It might be damaged when the electricity is turned on. 4. Please do a visual inspection on the printed-circuit-board before turning on the power supply, otherwise damage might happen due to problems such as a solder-bridge between the pins of the semiconductor device. Also perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as SP output pin (Pin A2, B1, D1, E2)-power supply pin short, SP output pin-GND short, or SP output-to-SP output-pin short (load short). 6. When using the LSI for model deployment or new products, perform fully the safety verification including the long-turn reliability for each product. 7. Please do not make it open, because the open SD pin (Pin B3) is not fixed. SDE00028BEB 26 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: - Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. - Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805 |
Price & Availability of AN12959A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |